Design Verification Team Lead – Peripheral IP Group (UVM) – (6047)

We are looking for a hands on Design Verification Team Lead to drive verification of next-generation wired/wireless peripheral subsystems that power Snapdragon platforms. As a DV Team Lead in the Peripheral group, you will own verification of complex IPs and subsystems, define and execute a UVM based verification strategy, and lead a small team of talented engineers to first time right silicon. This role requires proven leadership experience and strong technical expertise.

What you’ll do: Define verification strategy, test plan, and coverage goals for complex peripheral IP and subsystem blocks Architect, develop, and maintain UVM& based constrained random verification environments Lead day to day activities of a small DV team: task planning, code and test plan reviews, mentoring, and technical guidance Drive debug of complex issues across RTL, testbench, and system level, working closely with design, emulation and validation teams Analyze and close functional and code coverage, drive quality metrics to tape out criteria Contribute to methodology and flow improvements across the Peripheral DV team

Minimum qualifications: BSc/MSc in Electrical/Computer Engineering or related field At least 7 years of hands on verification experience using UVM and SystemVerilog Proven experience in leading and managing a team Strong background in digital design and SoC/IP architecture Proven technical leadership: Prior experience leading or mentoring engineers or Demonstrated ability and motivation to lead a small DV team (e.g., ownership of major IP, driving cross‑functional efforts) High technical proficiency in: UVM testbench architecture (agents, sequences, scoreboards, coverage) Constrained random, coverage driven verification Debugging complex failures in large scale regressions Scripting (Python/Perl/Tcl/shell) in a UNIX/Linux environment

Preferred qualifications Experience with high speed peripherals (e.g., USB, PCIe, Display, SerDes, or similar I/O IP) Knowledge of low power, reset, and clock domain interactions at IP/SoC level Familiarity with regression management, metrics, and sign off criteria Experience working with global, cross site teams

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